1. Field of the Invention
The present invention relates to a digital multiplier, and particularly to a digital multiplier which multiplies a coded first digital signal by a coded second digital signal to output a coded third digital signal.
2. Description of the Background Art
Digital multipliers are fundamental circuits as amplifiers and attenuators are in analog circuits, and are widely used in digital signal processing circuits.
Digital multiplication is basically performed as shown in FIG. 10, by repeating shifts and additions, as is done in calculation with figures of decimal numbers. Therefore, the conventional digital multipliers are formed of AND gates and full adders.
FIG. 9 is a block diagram showing an example of a construction of a conventional array type digital multiplier. Referring to the figure, the digital multiplier receives digital signals X1 and X0 of 2 bits as multiplicands and digital signals R1 and R0 of 2 bits as multipliers to output digital signals Y3-Y0 of 4 bits which are products of the digital signals X1 and X0 and the digital signals R1 and R0. The digital multiplier shown in FIG. 9 comprises AND gates 61a-61d and full adders 62a-62d. Each full adder has a terminal Ci for receiving carry signals, a terminal Co for supplying the carry signals, a terminal S for supplying addition signals. The construction of the digital multiplier shown in FIG. 9 is extremely general and is well known to those skilled in the art, and thus specific structures and operations thereof will not be described.
In the digital multiplier shown in FIG. 9, a maximum propagation path for signals in which a propagation delay time of a signal becomes maximum is formed by a path extending through one AND gate and four full adders, i.e., a path from X0 through the AND gate 61a, the full adder 62a, the full adder 62b, the full adder 62c and the full adder 62d to Y3. Generally, in a digital multiplier of an array type of n x n bits, signals must pass through at the most (3n-2) unit circuits, which are formed of AND gates and full adders. Another prior art for increasing speed of signal propagation has employed an algorithm of Booth or a carry save method. In either case, since the digital multiplier is constructed using full adders, carry delay is caused, and a length of the maximum propagation path for signals increases as the bit number of the digital signal to be input increases.
Since the conventional digital multipliers in which the digital signals are multiplied together are constructed using full adders as described above, there has been problems such as carry delay and increase of lengths of the maximum propagation paths for signals. These problems become more serious as the bit numbers of the supplied digital signals increase. Even if one of the supplied digital signals is set at a fixed value, this causes any change in the maximum propagation path for the signals in the conventional digital multiplier. In order to increase an operation speed of the digital multiplier, a pipeline construction may be employed. However, this causes other problems such as complicated construction of circuits and increase of a circuit area. The operation speed may be increased by using a ROM table in which all the multiplication results obtained by combination of multipliers and multiplicands are stored. However, in this construction, as the bit number of the supplied digital signals increases, the circuit area increases in a form of an exponential function, and a read speed decreases.